Miniaturization of electronic products are driving the need for smaller size packages with high circuit density and more functionality. As such, there is a demand for higher packaging efficiency. The need for miniaturization motivates the use of advanced packages, such as wafer level chip scale packages (WLCSP). WLCSP are desired as it is about the same size or slightly larger than the die itself and therefore reduces the required board real estate compared to other types of packages. However, current WLCSP is susceptible to damage, such as crack and/or chipping which may be formed during wafer saw or package singulation. Such damage may cause the chip to fail to perform its desired function.
In view of the foregoing, there is a desire to provide reliable WLCSP as well as simplified and cost effective methods for forming these packages.